A light emitting diode is used as a light source of a backlight unit for a liquid crystal display used in a flat panel display such as a television set, a monitor or the like.
Optical element chips such as light emitting diodes or the like are mounted on a raw chip plate for optical devices. Unit optical devices are manufactured through a process of separating, namely sawing or dicing, the raw chip plate for optical devices.
As an example, Korean Patent Registration No. 1,541,035 (Patent Document 1) owned by the present applicant or the present inventor discloses a configuration of a raw chip plate which does not generate burrs in a process of separating, namely sawing or dicing, the raw chip plate into optical devices.
As illustrated in FIG. 1, a raw chip plate includes a plurality of conductive layers A and A′ laminated in one direction, at least one insulation layer B alternately laminated with the conductive layers A and A′ to electrically isolate the conductive layers A and A′, and a cavity D formed in a groove shape at a predetermined depth in a region of an upper surface of the raw chip plate including the insulation layer B, the cavity D having an inclination angle θ.
Pursuant to a customer's request, there may be a need to use an optical element chip larger in size than the optical element chip illustrated in FIG. 1, under the condition that the overall size of a chip substrate and the size, depth and reflection angle of the cavity D formed in the chip substrate remains the same.
The optical element chip is positioned at the center of the cavity D. Due to the existence of the insulation layer B positioned at the left side on the basis of FIG. 1, there is a limit in the size of the optical element chip that can be employed.
In other words, if the insulation layer B is disposed as illustrated in FIG. 1 (if the insulation layer B is not further moved to the left side) in order to provide a wire bonding region for electrically interconnecting the optical element chip and the conductive layer A, a problem is posed in that the increase in the size of the optical element chip is very small.
In the case where the formation position of the insulation layer B on the chip substrate is further moved to the left side (on the basis of the cross section illustrated in FIG. 2) in order to mount an optical element chip having a larger size on the cavity D, the following problem is posed.
Specifically, when the size of the optical element chip is increased in the related art as illustrated in FIG. 2, the formation position of the insulation layer B needs to be moved to the left side. In this case, there is posed a problem in that a wire bonding region for electrically interconnecting the optical element chip and the conductive layer A becomes quite narrow.
Under the circumstances, a demand has existed for the technical development of a chip substrate capable of not only increasing the size of the optical element chip and sufficiently providing a wire bonding region for electrically interconnecting the optical element chip and the conductive layer A.